Self-aligned fabrication process for gaas mesfet devices

Details Self-aligned fabrication process for gaas mesfet devices Self-aligned fabrication process for gaas mesfet devices

H - Electricity

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356/149

H01L 21/425 (2006.01) H01L 21/285 (2006.01) H01L 21/324 (2006.01) H01L 21/338 (2006.01)

Patent

CA 1252226

Abstract of the Disclosure A self-aligned process for fabricating a GaAs semiconductor MESFET by depositing a layer of tungsten over the GaAs substrate, and ion implanting the substrate to provide channel doping. A gate composed of a conductive refractory material is deposited and delineated on the tungsten layer, and source and drain regions are formed in the substrate using the gate as a mask. The resulting device is annealed and contacts are formed to the source and drain regions, and to the gate.

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