Self-aligned integrated circuits

Details Self-aligned integrated circuits Self-aligned integrated circuits

G - Physics

11

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356/73

G11C 11/40 (2006.01) G11C 11/24 (2006.01) G11C 11/35 (2006.01) H01L 21/8242 (2006.01) H01L 27/07 (2006.01) H01L 27/108 (2006.01) H01L 29/06 (2006.01)

Patent

CA 1043467

SELF-ALIGNED INTEGRATED CIRCUITS ABSTRACT OF THE DISCLOSURE: Semiconductor integrated circuits, including, e. g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of a semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semi- conductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide- silicon nitride, the dopant may be ion implanted through the insulating medium to form, e. g., the source and drain electrode of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e. g,, a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.

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