Self-aligned manufacture of fet

Details Self-aligned manufacture of fet Self-aligned manufacture of fet

H - Electricity

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L

356/75

H01L 21/425 (2006.01) H01L 21/265 (2006.01) H01L 21/311 (2006.01) H01L 21/338 (2006.01) H01L 29/80 (2006.01) H01L 29/812 (2006.01)

Patent

CA 1205922

ABSTRACT OF THE DISCLOSURE This specification discloses a self-aligned manufacturing method of a Schottky gate FET. This method comprises the steps: forming a gate metallic layer on a semiconductor substrate and a mask overhanged on the metallic layer; ion-implanting impurity ions into the semiconductor substrate using the mask to form a source/drain region; depositing an insulator on the gate metallic layer side surface and the other surface below the mask; directionally etching said deposited insulator using the mask to expose the source/drain region; depositing a source/ drain electrode using the mask; and removing the mask.

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