Self-aligned metal process for field effect transistor...

Details Self-aligned metal process for field effect transistor... Self-aligned metal process for field effect transistor...

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H01L 21/28 (2006.01) H01L 21/033 (2006.01) H01L 21/321 (2006.01) H01L 21/336 (2006.01) H01L 21/8242 (2006.01) H01L 29/41 (2006.01) H01L 29/76 (2006.01)

Patent

CA 1169585

SELF-ALIGNED METAL PROCESS FOR FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS Abstract A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the poly- crystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer is then FI9-80-016 removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes. A blanket layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed. FI9-80-016

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