Self-aligned metal silicide process for integrated circuits...

Details Self-aligned metal silicide process for integrated circuits... Self-aligned metal silicide process for integrated circuits...

H - Electricity

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H01L 21/82 (2006.01) H01L 21/02 (2006.01) H01L 21/225 (2006.01) H01L 21/285 (2006.01) H01L 29/04 (2006.01)

Patent

CA 1241770

SELF-ALIGNED METAL SILICIDE PROCESS FOR INTEGRATED CIRCUITS HAVING SELF-ALIGNED POLYCRYSTALLINE SILICON ELECTRODES ABSTRACT OF THE DISCLOSURE A process for fabricating self-aligned regions of metal silicide on bipolar integrated circuits having self-aligned polycrystalline silicon emitters and base contacts includes the steps of depositing a layer of polycrystalline silicon across the surface of the structure, patterning the polycrystalline silicon to define the emitters and base contacts as well as resistors and diodes, heating the structure to transfer desired conductivity dopants from the polycrystalline silicon into the underlying structure, forming a protective layer over those regions of the structure where metal silicide is not desired, depositing a layer of refractory metal across the entire structure, and reacting the refractory metal with the underlying silicon to form metal silicide.

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