Self-aligned micrometer bipolar transistor device and process

Details Self-aligned micrometer bipolar transistor device and process Self-aligned micrometer bipolar transistor device and process

H - Electricity

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H01L 27/04 (2006.01) H01L 21/74 (2006.01) H01L 21/762 (2006.01) H01L 29/08 (2006.01) H01L 29/10 (2006.01) H01L 29/732 (2006.01)

Patent

CA 1142266

A SELF-ALIGNED MICROMETER BIPOLAR TRANSISTOR DEVICE AND PROCESS Abstract A method for fabricating very high performance inte- grated circuit semiconductor devices. The method for de- vice fabrication disclosed is a self-aligned process. The device formed has small vertical as well as hori- zontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon sur- face through N+ subcollector region into the P substrate. The width of the deep trench is about 2 µm to 3.0 µm. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector sep- arates the base and collector contact. The surface of the isolation regions and the silicon where the transis- tor is formed is coplanar. The fabricated bipolar tran- sistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capa- citance which is a very important parameter in ultra- high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral con- tact to the active base. The P+ polysilicon layer which provides low base resistance is formed within the oxide isolation trenches, thus minimizing the parasitic capa- citance. The transistor active base is formed in place by a low dosage boron implantation made with its concen- tration peak below the emitter. The device formed thus will have a controllable narrow base width and a FI9-79-021 low external base resistance. Both are essential to the high performance devices. The emitter of this invention structure is separated from the P+ poly- silicon by a Si3N4/SiO2 composite dielectric layer. This dielectric separation ensures that electrons injected into the base do occur at the bottom of the emitter. The dielectric sleeve of the emitter also eliminates the sidewall hole current component nor- mally existing in conventional transistors. Thus, the bipolar transistors formed by the disclosed pro- cess have a high emitter injection efficiency and also have high transistor current gains. Further- more, the fabricated small geometry devices have planarized surface. The planarized device structure ensures the thin film covering which is critical to the integration of very small devices. FI 9-79-021

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