Self-aligned mos fabrication

Details Self-aligned mos fabrication Self-aligned mos fabrication

H - Electricity

01

L

356/196

H01L 21/22 (2006.01) H01L 21/263 (2006.01) H01L 21/31 (2006.01) H01L 21/762 (2006.01) H01L 21/764 (2006.01) H01L 21/8242 (2006.01)

Patent

CA 1157964

PHXA 1047 17 9.2.81 "ABSTRACT": "Self-aligned MOS fabrication". A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of poly- silicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS tran- sistor, such as the source. Dy selectivity etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor- one capacitor memory cell or a plu- rality of MOS transistors can be fabricated.

379593

Affiliated with

Also associated with

Rating

Self-aligned mos fabrication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned mos fabrication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned mos fabrication will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-503378