Self-aligned narrow gate mesfet process

Details Self-aligned narrow gate mesfet process Self-aligned narrow gate mesfet process

H - Electricity

01

L

356/140, 356/153

H01L 21/36 (2006.01) H01L 21/338 (2006.01) H01L 29/812 (2006.01)

Patent

CA 1118113

ABSTRACT OF THE INVENTION A method of making a narrow gate MESFET including the steps of placing a layered mask of nitride and polysilicon over a channel region for self-aligning in a substrate, oxidizing and then removing the polysilicon to reduce the remaning polysilicon width, etching the nitride to the polysilicon width, oxidizing the substrate where the nitride defines the gate therein, removing the nitride, and depositing metal on the gate to form the MESFET schottky gate. Advantages of the improved MESFET include a relatively higher device gain, greater IC density, a self-aligned Schottky gate, controllable minimum series resistance, a relatively short channel using a conventional photo process, and a n- resistor that may be easily simultneously fabricated therewith.

323827

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