Self-aligned semiconductor method

Details Self-aligned semiconductor method Self-aligned semiconductor method

H - Electricity

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H01L 21/312 (2006.01) H01L 21/027 (2006.01) H01L 21/265 (2006.01) H01L 21/266 (2006.01) H01L 21/321 (2006.01) H01L 21/336 (2006.01) H01L 21/47 (2006.01) H01L 29/06 (2006.01)

Patent

CA 1138123

1 PHB. 32 629, ABSTRACT: Method for self-aligned manu- facturing of an insulating layer on top of a doped region surrounding a semiconductor circuit element. According to the invention first an insulating layer is provided on a semiconductor body portion. Then a first masking layer is provided on top of part of the insulating layer. The doped region is formed by ion implantation through the insulating layer in the semiconductor surface not covered by the first masking layer. Then a second masking layer is provided on the first masking layer and on the insula- ting layer. After that the first masking layer with the portion of the second masking layer on top of it is removed. Then the uncovered portion of the insulating layer is removed after which in the so obtained free semiconductor surface area the semiconductor circuit is provided. This preferably is an IGFET, the insulating layer being the field oxide, and the doped region being a channel stopper.

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