H - Electricity – 03 – K
Patent
H - Electricity
03
K
328/87, 328/88
H03K 5/135 (2006.01) G06F 1/04 (2006.01) G06F 1/12 (2006.01) H03K 5/151 (2006.01)
Patent
CA 1253926
SELF-CHECKING, DUAL RAILED, LEADING EDGE SYNCHRONIZER ABSTRACT The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregu- larities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true com- plement relationship.
508763
Chandran Srikumar R.
Walker Mark S.
Smart & Biggar
Tandem Computers Incorporated
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