Self checking dynamic memory system

Details Self checking dynamic memory system Self checking dynamic memory system

G - Physics

11

C

354/223

G11C 29/00 (2006.01) G06F 11/10 (2006.01) G11C 29/04 (2006.01) G11C 29/42 (2006.01) G11C 29/44 (2006.01)

Patent

CA 1107862

SELF CHECKING DYNAMIC MEMORY SYSTEM Abstract of the Disclosure The storage space of the instant system is considered, for refresh purposes, to contain 512 groups of 26 bit digital words with each group containing 128 such words. Memory refresh is implemented by sequen- tially refreshing the groups of digital words at the rate of one group every 2.8 microseconds, giving an ex- pected total memory refresh time of approximately 1.43 milliseconds. A particular digital word from each group of digital words refreshed is read from the memory and transmitted to a parity check circuit which generates fault signals for any digital word having faulty parity. At the end of each of the approximately 1.43 millisecond refresh cycles, the particular word read from each group refreshed is changed so that at the end of 128 full re- fresh cycles (approximately 184 milliseconds), the parity of every digital word in the memory has been checked. further, circuitry is provided to store the location of the first failing digital word in a trap register in response to an indication of faulty parity.

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