Self-correcting memory circuit

Details Self-correcting memory circuit Self-correcting memory circuit

G - Physics

11

C

354/241

G11C 29/00 (2006.01) G06F 11/14 (2006.01)

Patent

CA 1070432

SELF-CORRECTING MEMORY CIRCUIT ABSTRACT OF THE DISCLOSURE A circuit for storing data in a random access memory containing one defective bit per word. A separate read-only memory device or programmable logic array is pro- vided to produce an interrupt bit whenever a memory location containing a defective bit is addressed, where a defective bit is defined as one that is stuck at 1 or stuck at 0. If an interrupt bit is generated the data word is read out from memory and compared to the original, If an equality exists, nothing further is required. If there is an inequal- ity the data word is complemented and stored, and a flag bit is set. When data is read from memory, if the flag bit is set, the data word is complemented again before being used.

271161

Affiliated with

Also associated with

Rating

Self-correcting memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-correcting memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-correcting memory circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-716798