Self-correcting, solid-state mass memory organized by bits...

Details Self-correcting, solid-state mass memory organized by bits... Self-correcting, solid-state mass memory organized by bits...

G - Physics

06

F

354/224

G06F 13/00 (2006.01)

Patent

CA 1133143

ABSTRACT OF THE DISCLOSURE 1. A self-correcting, solid-state mass-memory, organized by bits and with reconfiguration capability for a stored program control system, comprising a processing system interfaced with the mass memory through a controller, said memory consisting of one or a plurality of memory modules and a control module at least, comprising a time base which generates timing and con- trol signals for memory operation, with shape and period var- iable according to the operation, an addressing control circuit which generates the addresses for memory reading and writing, in- put-output means which send the data towards the memory or the controller and a self-correcting logic which controls the right operation of the memory, corrects and signals to the controller the possible memory errors, said memory being characterized in that each memory module is intended to store a bit of a plu- rality of words consisting of information and redundancy bits to be used for self-correction operations and comprises: - a plurality of memory integrated circuits obtained by charge- coupled technology and consisiting of blocks of shift re- gisters organized in serial-parallel-serial configuration, each block being able to he addressed randomly and at the same time as the blocks of equal position in all the corres- ponding circuits of all the memory modules and containing a plurality of cells to be addressed in sequence; - data input-output means; - means for receiving from the control module or each control module and sending to the integrated circuits of the memory module the timing, addressing and control signals.

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