Self-synchronising descrambler

Details Self-synchronising descrambler Self-synchronising descrambler

H - Electricity

04

K

340/70

H04K 1/00 (2006.01) H04L 25/03 (2006.01)

Patent

CA 1242011

ABSTRACT A SELF-SYNCHRONISING DESCRAMBLER A self-synchronising descrambler for high bit rates having a number of parallel operating descrambler stages, each of which represents the series connection of first and second modulo-2-adders (A1, A2) and at least one shift register stage (SR1, SR2). For the suppression of short periods, between the first and second modulo- 2-adders a third modulo-2-adder can be interposed and means provided to invert at least one bit of the through- going signal via said third modulo-2-adder on the occur- rence of short periods. Fig. 1

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