Semiconductor chip package

Details Semiconductor chip package Semiconductor chip package

H - Electricity

01

L

356/9

H01L 23/52 (2006.01) H01L 23/538 (2006.01)

Patent

CA 1182582

ABSTRACT OF THE DISCLOSURE AN IMPROVED SEMICONDUCTOR CHIP PACKAGE A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by persona- lized surface wiring and preset subsurface conduc- tors.

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