Semiconductor device and method of forming a semiconductor...

H - Electricity – 01 – L

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H01L 29/06 (2006.01) H01L 21/331 (2006.01) H01L 27/088 (2006.01) H01L 29/739 (2006.01) H01L 29/78 (2006.01) H01L 21/762 (2006.01) H01L 29/20 (2006.01) H01L 29/24 (2006.01)

Patent

CA 2423028

A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane )16) which has opposed top and bottom surfaces (15, 17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

L'invention concerne un dispositif de puissance semi-conducteur (10) qui comporte une région active comprenant une région de dérive (20). Au moins une partie de la région de dérive (20) comporte une membrane (16) dotée de surfaces inférieure et supérieure opposées (15, 17). Dans un mode de réalisation, la surface supérieure (15) de la membrane (16) comporte des terminaux électriques qui lui sont connectés directement ou indirectement pour qu'une tension soit appliquée latéralement sur la région de dérive (20). Dans un autre mode de réalisation, au moins un terminal électrique est connecté directement ou indirectement à la surface supérieure (15) et un autre terminal électrique est connecté directement ou indirectement à la surface inférieure (17) pour qu'une tension soit appliquée verticalement sur la région de dérive (20). Dans ces modes de réalisation, la surface inférieure (17) de la membrane (16) ne comporte pas de substrat semi-conducteur adjacent.

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