Semiconductor device including a floating gate memory cell...

H - Electricity – 01 – L

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H01L 29/788 (2006.01) H01L 27/115 (2006.01) H01L 29/15 (2006.01)

Patent

CA 2650809

A semiconductor device may include a semiconductor substrate (21) and at least one non- volatile memory cell. The at least one memory cell may include spaced apart source and drain regions (26,27), and a superlattice channel (25) including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate (37) may be adjacent the superlattice channel, and a control gate (39) may be adjacent the second gate (38) insulating layer.

L'invention concerne un dispositif à semi-conducteur qui peut comporter un substrat à semi-conducteur (21) et au moins une cellule de mémoire rémanente.Les cellules de mémoire peuvent comporter des zones source et de drain séparées (26, 27), et un canal de super-réseau (25) comportant plusieurs groupes de couches empilés sur le substrat à semi-conducteur entre les zones source et de drain. Chaque groupe de couches du canal de super-réseau peut comporter plusieurs monocouches à semi-conducteur de base empilées définissant une partie à semi-conducteur de base avec, au-dessus, une couche de modification de bande d'énergie, qui peut comporter au moins une monocouche non-semiconductrice insérée dans un réseau cristallin de parties à semi-conducteur de base contiguës. Une grille flottante (37) peut jouxter le canal de super-réseau, et une grille de commande (39) peut jouxter la couche isolante de la seconde grille (38).

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