Semiconductor device utilizing memory cells with sidewall...

Details Semiconductor device utilizing memory cells with sidewall... Semiconductor device utilizing memory cells with sidewall...

G - Physics

11

C

352/81

G11C 11/08 (2006.01) G11C 11/35 (2006.01) G11C 11/404 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1118892

Abstract of the Disclosure A semiconductor memory device including a substrate supporting an array of memory cells wherein each cell comprises a single recess in the sur- face of the device whose lower end penetrates into a buried bit line within the substrate. Parallel and spaced apart word lines of conductive material formed on the surface of the device and oriented perpendicular to the buried bit lines extend into the recesses of the memory cells. For each recess a thre- shold barrier around its upper end and a diffusion barrier around its lower end adjacent the buried bit line combine to form a charge storage area in the material forming the walls of the recess, so that the portion of a word line within each recess provides a gate for modulating the flow of charge to and from the bit line during read and write oppressions.

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