Semiconductor embedded layer technology including permeable...

Details Semiconductor embedded layer technology including permeable... Semiconductor embedded layer technology including permeable...

H - Electricity

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H01L 29/40 (2006.01) H01L 21/20 (2006.01) H01L 21/335 (2006.01) H01L 21/74 (2006.01) H01L 23/482 (2006.01) H01L 23/52 (2006.01) H01L 23/535 (2006.01) H01L 29/772 (2006.01) H01L 29/92 (2006.01)

Patent

CA 1165011

ABSTRACT OF THE DISCLOSURE A permeable base transistor including a metal base layer embedded in a semiconductor crystal to separate collector and emitter regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening through which the crystal semiconductor joins the collector and emitter regions. Ohmic contacts are made to the emitter and collector regions. The width of all openings in the base layer is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer is in the order of 10% of this zero bias depletion width, As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer, is lowered sufficiently to permit substan- tial increase in the barrier limited current flow from the collector to emitter. A method of fabricating this transistor as well as methods for forming integrated cir- cuit structures including the transistor are also dis- closed.

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