Semiconductor fabrication method for improved device yield

Details Semiconductor fabrication method for improved device yield Semiconductor fabrication method for improved device yield

H - Electricity

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356/92

H01L 21/70 (2006.01) H01L 21/265 (2006.01) H01L 21/322 (2006.01)

Patent

CA 1090005

SEMICONDUCTOR FABRICATION METHOD FOR IMPROVED DEVICE YIELD Abstract of the Disclosure A method for fabricating bipolar semiconductor devices of large scale integration in which the forma- tion of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.

281576

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