Semiconductor integrated circuit and a method for designing...

Details Semiconductor integrated circuit and a method for designing... Semiconductor integrated circuit and a method for designing...

H - Electricity

01

L

356/146

H01L 21/44 (2006.01) H01L 27/02 (2006.01) H01L 27/04 (2006.01)

Patent

CA 1219380

84P03994/T95 ABSTRACT The packing density of an logic LSI based on standard cell methodology is increased by partially overlapping two adjoining cells so as to have common terminal regions to be connected to the wirings for supplying power. To this end, the pattern of the terminal region at a side edge in the direction along row of the cells is standardized of its shape, size and position in each cell, and registered in the cell library of a CAD system, together with a newly introduced additional sign to indicate the region to be overlapped during chip design operation using a display.

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