H - Electricity – 03 – K
Patent
H - Electricity
03
K
328/130
H03K 19/00 (2006.01) H03K 19/173 (2006.01)
Patent
CA 2033220
ABSTRACT OF THE DISCLOSURE In a semiconductor integrated circuit, upstream slave mode logic devices are informed successively of the completion of configuration for each slave mode logic device through a data line connected to the slave side, and a master mode logic device is finally informed of the completion of the configuration for all slave mode logic devices. Hereby, generation of a basic clock for the master mode logic device is controlled without use of a large-scaled circuit such as a pulse counter. Additionally, period of the clock supplied from said master mode logic device to each slave mode logic device is temporarily changed upon the completion of the configuration for all slave mode logic devices to inform each slave mode logic device of the completion of the configuration of all slave mode logic devices. - 25 -
Kawasaki Steel Corporation
Robic
Yoneda Masato
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