H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128
H01L 21/322 (2006.01) H01L 21/316 (2006.01) H01L 21/768 (2006.01) H01L 21/82 (2006.01) H01L 21/8234 (2006.01)
Patent
CA 1226073
- 14 - SEMICONDUCTOR INTEGRATED CIRCUITS GETTERED WITH PHOSPHORUS Abstract For achieving dense packing of MOS transistors at the top surface of a silicon semiconductor body, second level metallization including arsenic doped polysilicon contacts are used in conjunction with a phosphorus gettering step at a time when the top surface is sealed against the introduction of phosphorus by an undoped sacrificial glass layer, i.e., which is essentially free of phosphorus. The second level metallization is thereafter completed by coating the polysilicon with a high conductivity metal, such as aluminum. During the gettering, the polysilicon contacts are insulated from the first level metallization by a planarized glass layer doped with phosphorus to a concentration below the saturation level of phosphorus in the glass.
488669
Dalton John V.
Orlowsky Kenneth J.
Sinha Ashok K.
American Telephone And Telegraph Company
Kirby Eades Gale Baker
LandOfFree
Semiconductor integrated circuits gettered with phosphorus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuits gettered with phosphorus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuits gettered with phosphorus will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1269897