H - Electricity – 01 – L
Patent
H - Electricity
01
L
328/127, 356/30
H01L 27/00 (2006.01) H01L 27/02 (2006.01) H01L 27/07 (2006.01) H01L 27/085 (2006.01) H01L 29/739 (2006.01)
Patent
CA 1118531
Abstract of the disclosure A semiconductor integrated logic circuit comprises a load transistor having a carrier injecting region and a carrier extracting region and an inverter transistor having a source region, drain regions, channel regions each connected between the source region and each of the drain regions, and gate regions defining the respective channel regions therebetween. The extracting region is merged into the gate regions, The channel regions have such dimesions and an impurity con- centration that the channels are closed with depletion layers extending from the gate regions at zero gate voltage. The gate regions constitute a logic input and the drains constitute logic outputs. The zero gate voltage renders the channels non- conductive and the raised voltage renders the channels conduc- tive, thus realizing an inverter circuit useful for wired logics.
281923
Mochida Yasunori
Nishizawa Jun-Ichi
Nonaka Terumoto
Yoshida Takashi
Marks & Clerk
Nippon Gakki Seizo Kabushiki Kaisha
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