Semiconductor memory

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G11C 11/34 (2006.01) G11C 5/06 (2006.01) G11C 11/408 (2006.01) G11C 11/4096 (2006.01) G11C 11/4097 (2006.01)

Patent

CA 1199724

- 1 - Abstract A semiconductor memory has a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction. Memory cells are arranged at the points of intersection between the divided sub lines and the word lines. Common input/output lines are disposed in common to a plurality of such sub lines. The common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder. The arrangement provides a semiconductor memory having large storage capacity and high packaging density combined with a high signal to noise ratio and high reliability.

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