Semiconductor memory

Details Semiconductor memory Semiconductor memory

G - Physics

11

C

352/41, 352/81.1

G11C 11/36 (2006.01) G11C 5/02 (2006.01) G11C 7/12 (2006.01) G11C 8/02 (2006.01) G11C 8/06 (2006.01) G11C 8/10 (2006.01)

Patent

CA 1219369

ABSTRACT An electronic device is provided which includes first and second memory arrays, each capable of storing data at locations therein, and an address decoder positioned between the first and second memory arrays for decoding address signals input thereto and corresponding to the locations. The address decoder is advantageously configured as a set of ISL gates or MESFET logic gates. If is further advantageous to form the memory arrays of Schottky diodes which, when employed with the ISL configura- tion for an address decoder, utilizes the same Schottky diode in the memory arrays as are utilized in the ISL gates. A further refinement provides a precharged circuit for each bit line.

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