Semiconductor memory cell margin test circuit

Details Semiconductor memory cell margin test circuit Semiconductor memory cell margin test circuit

G - Physics

01

R

324/58.1

G01R 31/30 (2006.01) G01R 31/28 (2006.01) G11C 29/50 (2006.01)

Patent

CA 1184248

SEMICONDUCTOR MEMORY CELL MARGIN TEST CIRCUIT ABSTRACT OF THE DISCLOSURE A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (Vcc*) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (Vcc*) is the semiconductor memory circuit main supply source (Vcc) in normal operation but can be forced to a different voltage during the margin test.

395312

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