G - Physics – 11 – C
Patent
G - Physics
11
C
352/82.2, 352/82
G11C 11/40 (2006.01) H01L 27/10 (2006.01) H01L 27/108 (2006.01)
Patent
CA 1210865
SEMICONDUCTOR MEMORY DEVICE HAVING STACKED CAPACITOR-TYPE MEMORY CELLS ABSTRACT OF THE DISCLOSURE In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell comprises an electrode (E0), an insulating layer (6), and a counter electrode (E1). The elec- trode (E0) is connected electrically to a source or drain region of a transfer transistor and extends over a part of a word line (WL2) adjacent to a word line (WL1) serving a gate electrode of the transfer tran- sistor, at which part no memory cell is formed.
442622
Nakano Tomio
Sato Kimiaki
Takemae Yoshihiro
Fujitsu Limited
Mcfadden Fincham
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