G - Physics – 06 – F
Patent
G - Physics
06
F
354/224, 352/82
G06F 11/20 (2006.01) G06F 11/18 (2006.01) G11C 29/00 (2006.01)
Patent
CA 1172768
Abstract of the Disclosure In addition to a main memory device a spare memory device is provided. Both memory devices utilize word wires in common which are arranged to constitute matrix circuits together with groups of bit lines. When a bit error is contained in data read out from the main memory device, a correction circuit correcting the error and a register for storing the error are provided. An output of the register is used to switch a bit line from which the error has been detected to a corresponding bit line of the spare memory device.
398170
Inoue Junichi
Mano Tsuneo
Yamada Junzo
Macrae & Co.
Nippon Telegraph & Telephone Public Corporation
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