G - Physics – 11 – C
Patent
G - Physics
11
C
352/40
G11C 11/34 (2006.01) G06F 11/10 (2006.01) G11C 11/406 (2006.01) G11C 11/4063 (2006.01) G11C 29/48 (2006.01)
Patent
CA 1170766
SEMICONDUCTOR MEMORY FOR USE IN CONJUNCTION WITH ERROR DETECTION AND CORRECTION CIRCUIT ABSTRACT A semiconductor dynamic memory circuit (10) includes a memory cell array (38) which includes a plurality of memory cells which are accessed through row and column lines by operation of row and column clock chain signals. A strap (68) is provided to operate the circuit (10) as either a memory which is refreshed according to internally generated addresses or a memory which is refreshed in response to externally supplied memory addresses and is easily incorporated into a memory system which utilizes error detection and correction during the refresh operation. In the absence of the strap (68) a refresh signal (20)) refreshes cells of the array (38) in response to the address generated by an internal address counter (82). The circuit (10) accesses a given memory location when an externally supplied address is provided together with a RAS signal (12) and a CAS signal (16). When the strap (68) is incorporated into the circuit (10) the refresh signal (20) applied thereto causes the memory cell array (38 to be refreshed at the externally supplied address. The data within the memory cell array (38) is accessed in response to an externally supplied memory address, the RAS signal (12) and the CAS signal (16). The CAS signal (16) is inhibited in the absence of the RAS signal (12). The circuit (10) is used within a memory array (102) for reading out stored data together with error correcting bits while at the same time refreshing all of the memory circuits in the memory (102). An error detecting and correcting circuit (160) is provided to evaluate the data read out from the memory circuits and to provide a corrected data pattern when erroneous bits are detected.
378893
Kirby Eades Gale Baker
Mostek Corporation
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