Semiconductor memory having main word line and subword lines...

Details Semiconductor memory having main word line and subword lines... Semiconductor memory having main word line and subword lines...

G - Physics

11

C

G11C 8/00 (2006.01) G11C 7/10 (2006.01) G11C 11/4096 (2006.01) H01L 27/108 (2006.01)

Patent

CA 2195836

In a memory in which a memory cell array 200 and a subword drive circuit SWD are alternately arranged in a row direction in addition to an SA array 170 and a cross portion (SWC) alternately arranged, there are arranged an interface circuit 100 between a global I/0 line GIOT/B and a local I/O line LIOT/B in a first cross portion SWD1, nMOSs Q2, Q4, and Q5 of an SA control circuit in a second cross portion SWC2, and pMOSs Q1 and Q3 of the SA control circuit in a third cross portion SWC3.

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