Semiconductor memory redundant element identification circuit

Details Semiconductor memory redundant element identification circuit Semiconductor memory redundant element identification circuit

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01) G11C 29/00 (2006.01) G11C 29/44 (2006.01)

Patent

CA 1203575

SEMICONDUCTOR MEMORY REDUNDANT ELEMENT IDENTIFICATION CIRCUIT ABSTRACT OF THE DISCLOSURE A test circuit (10) for a semiconductor memory is provided. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).

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