Semiconductor memory using multiple level storage structure

Details Semiconductor memory using multiple level storage structure Semiconductor memory using multiple level storage structure

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G11C 7/00 (2006.01) G11C 11/40 (2006.01) G11C 11/56 (2006.01) G11C 19/00 (2006.01)

Patent

CA 1224567

- 1 - Abstract: A semiconductor memory for reading and writing stored charges in an X-Y address system has a plurality of memory cells each consisting of one capacitance element and one MOS-FET in matrix. The invention is characterized by the use of a multiple level storage structure for reading and writing of at least three multi-level data stored in the capacitance elements. This result is achieved by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of the MOS-FET.

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