Semiconductor metallisation system

Details Semiconductor metallisation system Semiconductor metallisation system

H - Electricity

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K

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H05K 1/14 (2006.01) H01L 21/768 (2006.01) H01L 23/528 (2006.01) H01L 27/02 (2006.01) H05K 3/00 (2006.01)

Patent

CA 1102923

ABSTRACT: The invention relates to a wiring system for semiconductor circuits in which a first metallisation pattern is sunk in a layer of oxide which may be sunk if desired and a second metallisation pattern which overlies the first is contacted to the first metallisation pattern and to the-semiconductor regions via contact holes. The invention provides important advantages in that it enables more reliable and flatter metallisations which thus present possibili- ties for multilayer wiring systems. In addition the invention relates to a method of realising a multi- layer wiring in which one mask is saved as compared with prior art methods. -25-

298553

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