Semiconductor package

H - Electricity – 05 – K

Patent

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Details

356/143, 356/6,

H05K 1/02 (2006.01) H01L 23/047 (2006.01) H01L 23/14 (2006.01) H01L 23/495 (2006.01) H05K 1/05 (2006.01) H05K 1/03 (2006.01) H05K 3/42 (2006.01)

Patent

CA 1212484

-39- ABSTRACT A chip carrier 90 and a process of assembling a chip carrier are disclosed, The carrier used for mounting a chip comprises a copper or copper base alloy component 92 having a thin refractory oxide layer 93 on 2 surface thereof. The surface and the oxide layer have an indentation formed therein for receiving the chip 102. A metallic circuit pattern 98 for electrical connection to the chip is bonded to the oxide layer and insulated from the copper or copper base alloy by the refractory oxide layer. A seal 104 is provided for enclosing the chip to the indentation. Another embodiment of the invention includes a circuit board structure comprising a circuit board device 24 having a first coefficient of thermal expansion. A chip carrier 90 is provided having a second coefficient thermal expansion of substantially the same value as the first coefficient of thermal expansion. The chip carrier has electrical leads 100 soldered to the circuit board whereby thermal cycling of the circuit board structure does not substantially stress the bond between the solder, leads and circuit board. Other embodiments of the present invention include both leadless and leaded hermetic semi- conductor packages and innovative relationships between the packages and printed circuit boards.

419849

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