Semiconductor package, semiconductor device, electronic...

Details Semiconductor package, semiconductor device, electronic... Semiconductor package, semiconductor device, electronic...

H - Electricity

01

L

H01L 21/60 (2006.01) H01L 21/56 (2006.01) H01L 23/12 (2006.01) H01L 23/31 (2006.01) H01L 23/485 (2006.01) H01L 23/525 (2006.01)

Patent

CA 2340677

An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

L'invention concerne une couche isolante (3) comprenant une ouverture (3a) correspondant à une pastille d'électrode (2). On forme alors une saillie (4) de résine sur la couche isolante (3), puis une couche de résist dont les évidements correspondent à cette ouverture (3a), à la saillie (4) et à la zone qui les sépare. Finalement, on forme une couche plaquée de cuivre (6) par électrodéposition en utilisant la couche de résist comme masque.

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