Semiconductor static memory device

Details Semiconductor static memory device Semiconductor static memory device

G - Physics

11

C

352/82.1

G11C 11/40 (2006.01) G11C 8/12 (2006.01) G11C 8/14 (2006.01) G11C 11/418 (2006.01) G11C 11/419 (2006.01)

Patent

CA 1234628

ABSTRACT OF THE DISCLOSURE A semiconductor static memory device in which the power consumption is minimized. The memory cells are grouped in column blocks and rows. A NAND gate is provided for each such group, with the output of the NAND gate being coupled to the ground terminals of the cells in its group. The input terminals of the NAND gates receive respective row and column block selection signals. potential generator is provided in each cell for boosting the potential of the ground terminal of the cell above the potential of the word line, less a threshold voltage of one of the access transistors of the cell, when the corresponding block is not selected. The NAND gates sets the potential of the ground terminal at ground voltage when both the column block and word line signals applied thereto are in the high state.

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