H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/02 (2006.01) H01L 21/461 (2006.01) H01L 21/74 (2006.01)
Patent
CA 2425289
A method for processing a low ohmic contact structure to a buried conductive layer in or below a device layer forming part of a semiconductor component is presented, whereby first a highly doped region within said device layer reaching said buried conductive layer is realised, this being followed by a step of etching a trench through said highly doped region to a final depth which extends at least to the semiconductor substrate underneath said buried conductive layer. In a variant method this trench is first pre- etched until a predetermined depth, before the highly doped region is provided. A semiconductor structure which is realised by these methods is described as well.
Boonen Sylvie
Colson Paul Frans Marie
de Backer Eddy
de Pestel Freddy Marcel Yvan
Moens Peter Dominique Willem
Ami Semiconductor Belgium Bvba
Smart & Biggar
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