Semiconductor structures and methods for manufacturing such...

Details Semiconductor structures and methods for manufacturing such... Semiconductor structures and methods for manufacturing such...

H - Electricity

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356/151

H01L 21/31 (2006.01) H01L 21/76 (2006.01) H01L 21/762 (2006.01) H01L 21/764 (2006.01) H01L 27/02 (2006.01)

Patent

CA 1090006

SEMICONDUCTOR STRUCTURES AND METHODS FOR MANUFACTURING SUCH STRUCTURES Abstract of the Disclosure Semiconductor integrated circuit structures and manufac- turing methods wherein isolation grooves are etched into a semiconductor body by first bringing an anisotropic etchant in contact with portions of the surface of the body which are exposed by windows formed in an etch-resistant mask to form grooves with side walls which intersect the surface at acute angles. Next, an isotropic etchant is brought in contact with the walls of the etched grooves to remove portions of the body which are underneath the etch-resistant mask such that the mask extends over the side walls of the resulting grooves, the bottom walls of such grooves are disposed under the windows and the side walls maintain acute angle intersection with the surface. Junction isolation regions are formed by ion implanting particles into the bottom walls of the grooves, the mask shielding the side walls from such particles. This self- aligning process accurately controls the placement o-f the junction isolation regions and thereby reduces the depth required for the grooves in providing dielectric isolation. Because the grooves have side walls which intersect the surface at acute angles, and because the grooves are relatively shallow because of the addition of accurately placed junction isola- tion regions, subsequent metallization processing is more readily controllable.

292266

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