Semiconductor wafer fabrication

Details Semiconductor wafer fabrication Semiconductor wafer fabrication

H - Electricity

01

L

356/134

H01L 23/52 (2006.01) H01L 21/768 (2006.01) H01L 23/522 (2006.01)

Patent

CA 1222575

ABSTRACT OF THE DISCLOSURE A method of producing a via in the fabrication of a semiconductor wafer is disclosed. Vias are used in semiconductor wafer fabrication as a means of pro- viding electrical connections between different layers of the water. The walls of known vias are difficult to coat reliably with metal because, particularly in the case of fabrication processes aimed at small line widths, the vias must be kept within certain size limits and neces- sarily have vertical walls. The method described involves the formation in a layer of dielectric material of two communicating passageways. One passageway has sloping walls to facilitate metal coating. The other passageway has substantially vertical walls, thus keeping the via within required dimensions at the region of the wafer to which a connection is to be made. The two passageways are produced in separate process steps, a non-erodable layer being used to define the via.

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