Sequential chip select decode apparatus and method

Details Sequential chip select decode apparatus and method Sequential chip select decode apparatus and method

G - Physics

06

F

354/241

G06F 13/00 (2006.01) G06F 12/04 (2006.01) G06F 12/06 (2006.01)

Patent

CA 1159154

ABSTRACT OF THE DISCLOSURE A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic mem- ory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multi- word bus eliminating any delay in address incrementing.

367804

Affiliated with

Also associated with

Rating

Sequential chip select decode apparatus and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sequential chip select decode apparatus and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sequential chip select decode apparatus and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-769470