Sequential logic integrated circuit for pcm compression

Details Sequential logic integrated circuit for pcm compression Sequential logic integrated circuit for pcm compression

H - Electricity

04

B

354/103

H04B 14/04 (2006.01) H03M 7/50 (2006.01)

Patent

CA 1237197

ABSTRACT A sequential logic circuit for providing PCM compression in an integrated circuit includes a first shift register having both serial and parallel outputs for receiving an uncompressed PCM word having a sign bit followed by a variable number of zeros and then a number of significant bits, a second shift register for outputting a compressed PCM word, a time base generating bit rate clock signals for shifting said registers, a counting circuit for counting bits for so long as zeros are shifted serially out of the first register, after ignoring the sign bit, the counting circuit having a maximum count, and control logic for first enabling shifting of the first register until the zeros or an uncompressed word are exhausted or the maximum count of the counter has been reached, and then enabling the second register to receive in parallel for subsequent output, said sign bit, bits from the counter representing the count of the counter, and bits from the first register representing the significant bits. The circuit includes inverters to complement each alter- nate bit upon loading into the second register.

497156

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