Sequential word aligned address apparatus

Details Sequential word aligned address apparatus Sequential word aligned address apparatus

G - Physics

06

F

354/241

G06F 13/00 (2006.01) G06F 12/02 (2006.01) G06F 12/04 (2006.01)

Patent

CA 1159155

ABSTRACT OF THE DISCLOSURE A memory subsysem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The sub- system further includes an adder circuit, a pair of tri- state operated address register circuits and timing cir- cuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.

367807

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