Serial data rate detection systems

Details Serial data rate detection systems Serial data rate detection systems

H - Electricity

04

L

340/71

H04L 1/00 (2006.01) H04L 25/02 (2006.01)

Patent

CA 2025848

A system and method are described for bit rate detection in a serial data communication system, the system employing a data rate prompt of a pair of opposite value data bits which follow a series of idle bits. In a first embodiment a receiving port employs a clocked delay element and a set of data clock rates, each data clock rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate. The bit rate detection method comprises: clocking the delay element at the highest data clock rate, upon the sensing of one of the opposite value data rate prompt bits at the delay element, to step the value of the sensed bit into the delay element. After a predetermined number of data clock pulses have stepped the value of the sensed bit into the delay element, the system compares the bit value at an input to the delay element and the bit value in a bit position of the delay element. If the comparison indicates an equality of bit values, the delay element is clocked at a lower data clock rate until the comparing step indicates an inequality of bit values. At this point, the bit rate has been determined. Another embodiment is also described wherein a pair of counters are substituted for the delay element.

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