G - Physics – 06 – F
Patent
G - Physics
06
F
354/223
G06F 11/10 (2006.01) H03M 13/03 (2006.01) H03M 13/15 (2006.01)
Patent
CA 1155229
SERIAL ENCODING-DECODING FOR CYCLIC BLOCK CODES Abstract of the Disclosure Means for serially encoding and decoding cyclic block codes having minimal parity check bits and single error correcting capability are disclosed. Encoder comprises: serial shift and divide means for generating parity check bits to append to the data word and thereby form the channel word; input buffer for storing bits of the next channel word during evaluation of the parity bits of the previous word; and output buffer registers for storing bits of the channel word for eventual transmission. Certain registers are partitioned into a parallel arrange- ment of register segments of predetermined lengths so as to effect full loading of each segmented register prior to the request for transmission from each register. Decoder comprises: means for shifting and dividing the received word to generate the syndrome as well as iteratively shifted versions of the syndrome; means, alternating operation with the shifting and dividing means, for comparing the characteristic polynomial of the code with the iteratively shifted versions of the syndrome; and means for correcting, in response to a predetermined output from the comparing means, the received word by inverting the bit in the received word depending on the number of iterations performed in generating the iteratively shifted versions of the syndrome. The decoder comprises two substantially identical sections each having two modes of operations. The sections alternate modes of operation so that two contiguous blocks are processed during a given interval.
369078
Kirby Eades Gale Baker
Western Electric Company Incorporated
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