Serial information transfer protocol

Details Serial information transfer protocol Serial information transfer protocol

G - Physics

06

F

354/231

G06F 13/42 (2006.01)

Patent

CA 1225747

SERIAL INFORMATION TRANSFER PROTOCOL ABSTRACT An interconnecting transparent serial bus for extending a parallel CPU domain to a parallel peripheral module domain includes a bidirectional serial protocol for transferring information between the CPU and one or more peripheral module controllers, referred to as rack masters. Each rack master provides a parallel path to any number of peripheral modules associated therewith. Serial bus protocol includes a frame line, defining a synchronous information exchange interval; a clock line, for propagating a synchronous information clock signal during the information exchange interval; a sync line, for propagating a sync signal to identify one or more discrete asynchronous information fields during the information exchange interval; and a signal line for propagating data, address, and control information be- tween the CPU and its associated rack masters in serial fashion.

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