Serial-to-parallel/parallel-to-serial conversion engine

H - Electricity – 03 – M

Patent

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Details

H03M 9/00 (2006.01) G11C 7/10 (2006.01)

Patent

CA 2347230

A serial-to-parallel/parallel-to-serial conversion engine that provides a bi- directional interface between a serial and a parallel TDM highway. The serial-to-parallel data conversion device includes a serial data input interface that receives the serially received data and provides a received data word. A serial-to-parallel mapping circuit receives the received data word and generates memory write control and write address signals. A memory device includes a first port responsive to the memory write control signals and write address signals for writing the received data word into the memory device, and a second port responsive to memory read control and read address signals for reading data from the memory device. Output interface circuitry generates the memory read control and read signals, and receives output data from the memory device and reorders the bits of the parallel output data to provide the parallel data word.

L'invention concerne un moteur de conversion série-parallèle/parallèle-série qui comporte une interface bidirectionnelle entre un bus TDM série et un bus TDM parallèle. Le dispositif de conversion de données série-parallèle comprend une interface d'entrée de données série qui reçoit les données reçues en série et fournit un mot de données reçues. Un circuit de mappage série-parrallèle reçoit le mot de données reçues et génère des signaux de commande et d'adresse d'écriture de mémoire. Un dispositif à mémoire comprend d'une part un premier port qui répond aux signaux de commande et d'adresse d'écriture de mémoire afin d'écrire le mot de données reçues dans le dispositif à mémoire, et d'autre part un second port qui répond aux signaux de commande et d'adresse de lecture de mémoire afin de lire les données du dispositif à mémoire. Un circuit d'interface de sortie génère les signaux de commande et d'adresse de lecture de mémoire et reçoit les données de sortie du dispositif à mémoire, et réordonne les bits des données de sortie parallèles afin de fournir le mot de données parallèles.

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