Set association memory system

Details Set association memory system Set association memory system

G - Physics

11

C

354/241, 352/41

G11C 17/00 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1216370

ABSTRACT OF THE DISCLOSURE A memory system for use in a computer which in the preferred embodiment provides two megabytes of capacity per board (up to four boards) is disclosed. An ALU generates an address signal which selects a number of set locations in the main memory. Simultaneously, a portion of the address field is fed to a set association logic circuit for parallel processing. The set association circuit contains tag storage memories and comparators which store least recently used (LRU) values and compare these LRU values to bit values generated by the comparator. The set association process updates the stored LRU values and then selects the desired set from the sets addressed in the main memory. A hash function is also used to provide for dispersal of storage locations to reduce the number of collisions of frequently used addresses. Because of hardware implementation of hashing and LRU algorithm, a constant predetermined cycle time is realized since all accessing functions occur substantially in parallel. Several sets of data are accessed similtaneously while a set association process is performed which selects one of the accessed sets, wherein access time is reduced because of the parallel accessing.

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