Seu resistant sram using feedback mosfet

Details Seu resistant sram using feedback mosfet Seu resistant sram using feedback mosfet

G - Physics

11

C

G11C 11/00 (2006.01) G11C 11/412 (2006.01)

Patent

CA 2481066

A random access memory cell has first and second inverters each having an input and an output. The input of the first inverter is coupled to the out put of the second inverter by a Schottky-diode-free MOSFET. The input of the second inverter is coupled to the output of the first inverter.

Cette cellule de mémoire vive comporte deux onduleurs ayant, chacun, une entrée et une sortie. L'entrée du premier onduleur est couplée à la sortie du second par un transistor MOSFET sans diode Schottky. L'entrée du second onduleur est couplé à la sortie du premier.

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