Shift register latch arrangement for enhanced testability in...

Details Shift register latch arrangement for enhanced testability in... Shift register latch arrangement for enhanced testability in...

G - Physics

11

C

328/49, 324/58.1

G11C 19/00 (2006.01) G01R 31/28 (2006.01) G01R 31/3185 (2006.01) H03K 19/173 (2006.01)

Patent

CA 1260079

SHIFT REGISTER LATCH ARRANGEMENT FOR ENHANCED TESTABILITY IN DIFFERENTIAL CASCADE VOLTAGE SWITCH CIRCUIT ABSTRACT OF THE INVENTION A shift register latch (SRL) arrangement for testing a combinational logic circuit, producing true and complement outputs in nature, has two clocked DC latches and additional circuitry for providing an input: to the second latch. Clock signal trains and an extra TEST signal are used to control the SRL arrangement in different modes. In a first mode, one of the outputs from the combinational logic circuit is latched into the first latch and provided to a succeeding combinational logic circuit. In a second mode, a plurality of the SRL arrangements are interconnected together to form a shift register chain so that each latch acts as one position of the shift register chain. Further, in a third mode, the true and complement outputs of the combinational logic circuit are exclusive ORed and its result is latched into the second latch. During the third mode, output of the first latch is prevented from being latched into the second latch.

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